SVLab
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Research

Find out our research interests and on-going projects.

  • Last updated: Jul 18, 2021

    SMT-Based Model Checking for Signal Temporal Logic


  • Last updated: Sep 27, 2021

    PLCMC (Programmable Logic Controller Model Checker)


  • Last updated: Sep 27, 2021

    RTCL (Real-Time Control Langauge)


  • Last updated: Sep 27, 2021

    HYBRIDSYNCHAADL: Modeling and Formal Analysis of Virtually Synchronous CPSs in AADL


  • Last updated: Sep 27, 2021

    Utilizing SMT Solver with Abstraction and Interval Propagation for Neural Network Verification


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